FPGA Implementation of H.264 CAVLC Decoder Using High-Level Synthesis
نویسندگان
چکیده
منابع مشابه
Decoder FPGA Implementation
—The non-binary Low Density Parity Check (LDPC) codes over Galois Fields GF(q = 2) have evolved from the binary LDPC codes that are today an industry standard for channel coding. The performance of short block length codes is significantly higher for non-binary LDPC, at the cost of increased decoding complexity. The efficient decoder hardware implementation is still a challenging task. Most of...
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ژورنال
عنوان ژورنال: Image Processing & Communications
سال: 2017
ISSN: 2300-8709
DOI: 10.1515/ipc-2017-0009